1. Field of the Invention
The present invention relates to a method for forming an isolation region in a semiconductor device, and more particularly to a method for forming an isolation region in a semiconductor device which allows easy performance of a shallow trench isolation (hereinafter referred to “STI”) dry etching process and maximizes the isolation effect by reducing trench depth to a third of the conventional trench depth and performing a field stop implant process during the formation of an STI to implant a high density of impurity ions which results in an increase in field threshold voltage, and reduces damage of silicon by plasma through enlarging a field of an area which is more than 5 times as thick as an oxide film of an STI sidewall due to a doping density difference, wherein the area is an area into which a high density of impurity ions is implanted.
2. Description of the Prior Art
As generally known in the art, in addition to the advance of semiconductor technology, high speed operation and high integration of semiconductor devices are in progress. Accordingly, fine adjustment and a high integration of pattern have been necessarily required. These are required for a device isolation region, which has a wide area within a semiconductor device.
A number of methods are known for decreasing the size of an isolation region of isolating semiconductor devices, and correspondingly increasing the size of an active area of the semiconductor devices. A local oxidation of silicon (hereinafter referred to “LOCOS”) process has been widely employed to form the isolation region in a semiconductor device. The LOCOS process is commonly used because of its simplicity and excellent reproducibility.
However, the LOCOS process forms a “bird's beak” at an edge of the isolation region, which results in an increase in the size of the isolation region and generates a leakage current.
Accordingly, in order to solve the above problems of the LOCOS process, a method for forming a shallow trench isolation (STI) region has been proposed. The STI region has a narrow width and an excellent isolation property. A conventional method for forming an STI isolating region will be described with reference to FIG. 1.
FIG. 1 is a sectional view which illustrates a conventional method for forming a shallow trench isolation element isolating film.
As shown in FIG. 1, a buffer pad oxide film 2 and a pad nitride film 3 are sequentially formed on a silicon substrate 1. The pad nitride film 3 functions as an oxidization inhibiting film. Then, a photoresist film 4 is coated on the pad nitride film 3 to define an isolation forming region, and is patterned and selectively removed after an exposure and development processes. At this time, a deep ultra violet (DUV) light source having an excellent resolution is used for forming the photoresist film 4 so as to form an isolating region having a narrow width. Subsequently, with the patterned photoresist film 4 serving a mask, the pad nitride film 3 and the buffer pad oxide film 2 are sequentially etched by respectively predetermined depths, and then the silicon substrate 1 is etched by a predetermined depth to from a shallow trench (ST). The patterned photoresist film 4 is removed by a known method, and an insulating film (not shown) is buried in the ST. The pad nitride film 3 and the pad oxide film 2 formed on a surface of the silicon substrate 1 are removed by a method known in the art to form a complete STI region.
The conventional method for forming an STI region has excellent electric properties. However, since the conventional method has deep trenches, it is a great burden when performing dry etching. Since an aspect ratio (i.e., the ratio of depth to width) and a micro-loading effect are increased in the range of of up to 0.10 μm trench width, it is difficult to perform dry etching. As the trench becomes deeper, the aspect ratio of the dry etching is increased causing an isolation short.